1. Field of the Invention
The present invention relates to an image processing circuit for image-processing image data picked up with an image pickup device such as a digital still camera.
2. Description of the Background Art
FIG. 13 schematically illustrates the structure of a general digital still camera 100. As shown in FIG. 13, an image signal picked up with an image pickup device 105 such as a loaded CCD or CMOS sensor is A/D converted to a digital image signal and thereafter captured by an image processing part 106, to be subjected to various image processing such as pixel interpolation, color space conversion and contour correction. The image data subjected to the image processing is displayed on a finder of a liquid crystal monitor 109 or the like, stored in a memory card 110 or output to an external device such as a personal computer through an interface 111. Referring to FIG. 13, numeral 101 denotes an optical lens, numeral 102 denotes a color correction filter, numeral 103 denotes an optical LPF (low-pass filter), numeral 104 denotes a color filter array, and numeral 107 denotes a driving part driving/controlling the image pickup device 105 etc.
As shown in FIG. 14, the image signal picked up with the image pickup device 105 is converted to a digital image signal (CCD data) and thereafter temporarily stored in a raw image data buffer 108a of a built-in memory 108 (step 100). Then, a real-time processing unit (hereinafter abbreviated as RPU) 120 formed by hardware provided in the aforementioned image processing part 106 reads the raw image data stored in the raw image data buffer 108a, executes the aforementioned image processing such as pixel interpolation, color space conversion and edge enhancement in real time, and outputs and stores the processed data to and in a processed data buffer 108b (step 101). Then, a CPU (central processing unit) 121 reads the processed data from the processed data buffer 108b at an instructed timing, compresses the processed data with a temporary storage buffer 108c by software processing in the JPEG (joint photographic experts group) system or the like, and stores the compressed data in a storage medium 122 such as the aforementioned memory card 110.
While the recent digital still camera is miniaturized and reduced in weight, the aforementioned built-in memory 108 is formed by a DRAM (dynamic random access memory) or an SDRAM (synchronous DRAM) and the buffer areas 108a to 108c used in the built-in memory 108 are increased in scale to disadvantageously increase the cost for a chip as well as power consumption.
Either an interlacing (interlace scanning) system reading two fields forming a frame, i.e., an even field consisting of only even lines and an odd field consisting of only odd lines, at absolutely different temporal timings or a progressive (sequential scanning) sequentially reading respective lines is employed for the aforementioned image pickup device 105. If the interlacing system is employed, three to five lines including a current line and a plurality of precedent and subsequent lines must be simultaneously processed when the RPU 120 executes pixel interpolation, for example, and hence it is necessary to capture the even field after storing the odd field in the raw image data buffer 108a for thereafter converting both fields to progressive data and outputting the same to the RPU 120. Therefore, reduction of the scale of the buffer areas 108a to 108c of the built-in memory 108 is limited.